1. Field of the Invention
The present invention generally relates to processing of materials with a plasma and, more particularly, to selective plasma etching processes, especially as used in semiconductor device manufacture.
2. Description of the Prior Art
The art of semiconductor electronic device manufacture has become highly sophisticated in recent years to provide a wide range of electrical properties of the devices, often at very high integration density. Generally, device location and basic dimensions of electronic devices included in integrated circuits are defined by a lithographic process and, at the high integration densities currently possible and foreseeable, many subsequent processes are performed in a manner which is self-aligned or material-selective in order to develop structures at sizes smaller than the resolution of lithographic processes and/or avoid problems associated with possible overlay positional errors and mis-registration of plural lithographic patterning processes.
Further, at the current state of the art, many properties of electronic devices are controlled or established by the dimensions of various structures in the devices. For example, gate insulator thicknesses in field effect transistors have become relatively critical to switching speed, capacitive loading of circuits providing an input thereto, off-current leakage and the breakdown voltage which the gate must withstand without damage to the gate insulator. In general, when thickness dimensions are critical, it is preferred to achieve the desired dimension by an etching process for maximal accuracy. Such etching processes must generally be performed with etchants which are highly selective to the material (e.g. oxide) to be etched since protection of other surfaces with lithographically patterned resists may not be economically feasible or even possible.
High accuracy of such processes implies that the process must be highly controllable and repeatable with good uniformity. In the past and, to some extent at the present time, relatively slow processes have been tolerated to achieve the required accuracy and uniformity, particularly for research, application specific integrated circuits (ASICS) and other low-volume devices. However, the capability to determine the electrical properties of such structures with high reliability, consistency and manufacturing yield as well as acceptable economy is often limited, as a practical matter, by the tools used for processing the semiconductor material, usually in the form of a wafer. Such tools are often complex and of high precision. Therefore such tools are generally expensive to build and maintain. The principal expense of modern production integrated circuits is thus a portion of the cost of the tools used to produce them and, therefore, varies inversely with tool throughput. Accordingly, the use of faster processes is required for acceptable economy and unit cost.
To achieve faster processes for semiconductor manufacture, many processes have been developed which employ a plasma formed by inducing ionization of one or more selected materials in carefully regulated concentrations or pressures. For example, the etching process which is highly selective to oxide is generally performed using a gas such as Si(CF.sub.3).sub.x which, when ionized to form a plasma, provides silicon ions and CF.sub.3 radicals. The CF.sub.3 radicals are highly selective to the etching of silicon oxide, particularly in the presence of silicon ions.
However, by the same token, the speed of the etching process is highly dependent on the concentration of CF.sub.3 radicals and hence on the degree of ionization of the etchant gas. The degree of ionization of the etchant gas is, in turn, dependent on the amount of energy or strength of the electric field applied thereto.
It can be appreciated that a plurality of chips are formed concurrently on one or more wafers placed in a reactor vessel and the wafers can be of substantial dimensions. Therefore, for practical manufacturing processes, a highly uniform plasma must be developed over a wide area in order to avoid substantial variations in device performance and specifications across a wafer or even across a chip; either of which would be unacceptable in a production volume manufacturing application.
Unfortunately, known arrangements for producing a plasma do not provide adequately uniform application of energy or electrical fields to the process gas particularly at high plasma densities. In fact, known arrangements include antennas that invariably cause a substantial peak in voltage at about the center of a radius thereof. The voltage pattern can also be significantly affected by the geometry and materials of the reactor vessel as well as external fields.
The problem of process uniformity and high process speed is further complicated and high voltage levels required for high plasma densities by another incident of plasma chemistry referred to as gas cracking. In the above example in which Si(CF.sub.3).sub.x is used as an etchant, the CF.sub.3 radicals of the dominant etchant gas can be further broken down or "cracked" to yield free fluorine radicals. Fluorine radicals are not selective to oxide and, in fact, are observed to etch silicon and other silicon compounds somewhat preferentially to silicon oxide. (However, it should be appreciated that some small degree of gas cracking is considered to be beneficial to many etching processes and the rate at which they proceed to the degree the effects thereof can be predicted and compensated at low power and ionization levels.)
Therefore, the production of an excess of highly reactive fluorine ions by gas cracking effectively destroys the selectivity required for the process. Further, since gas cracking is not easily controllable and concentrations of fluorine ions cannot be easily monitored, the repeatability of etching of oxide to a desired thickness is also lost. In essence, the result is that the problem of gas cracking precludes the maximum plasma densities and maximum process speeds from being achieved or even closely approached for many plasma enhanced processes including the example of oxide etching discussed above. That is, if the amount of ionization is maintained below that at which excess gas cracking will occur, the average plasma density will be far below that which would provide a maximal or even economically acceptable process rate. Further, the rate at which the process proceeds will vary substantially across the wafer, possibly yielding inconsistent electrical properties of devices on a single chip, and device damage.
To develop the highest possible etch rates for other materials, so-called inductively coupled plasma (ICP) processes and tools capable of inductively heating electrons and developing high density plasmas (HDP) have been developed and are in widespread use for etching of both metal and polysilicon. However, such tools are not suitable for HDP etching of oxides. While HDP ICP tools are necessary for higher plasma densities and higher etch rates, HDP ICPs crack the fluorocarbon radicals in the dominant etchant gas as described above.
Rather, capacitively coupled parallel plate magnetrons and multi-frequency sources are often used for many advanced oxide etches even though they are incapable of approaching the plasma densities of HDP tools or producing reasonably or acceptably uniform plasma density distributions at more than moderate plasma densities. Such capacitively coupled tools provide stochastic heating of electrons. These stochastically heated electrons have a hot tail distribution of the electron energy distribution function (EEDF) which is greater than that of a Boltzmann distribution. The hot tail distribution is associated with reduced gas cracking levels, while producing the same ion density.
Several reports of research on ultra high frequency (UHF) high density plasma systems have been published over the last few years. It has been claimed in these reports that 500 MHz and 150 MHz systems were inductively coupled plasmas that provided, relative to HDP ICP systems of equal plasma densities, lower gas cracking, lower electron temperatures for the main body of the electrons, hot tail electrons in the EEDF and no transverse magnetic fields or ExB effects adjacent the wafer or target.
However, while all of these asserted qualities are desirable for an oxide etch system as well as other HDP systems, there has been no solution to lack of uniformity of plasma density distribution over an area of practical dimensions for semiconductor processing in production environments, particularly for an oxide etch process. Uniformity of plasma density and potential are particularly important not only as a matter of uniformity of oxide etching and the progress of other processes but to avoid damage to the devices being produced during the etching process since damaging currents are due to absolute plasma density changes rather than percentage changes. It can readily be appreciated that such damage, particularly in regard to gate oxides, can dramatically reduce manufacturing yields.